Recently, portable electronic equipment such as mobile telephones and non-volatile semiconductor memory media such as IC memory cards have been downsized, and there have been increasing demands for reducing the number of parts used in the equipment and media and downsizing thereof. Therefore, in the semiconductor industry, packaging technologies for integrated circuits (ICs) have been advancing to meet requirements for miniaturization and mounting reliability.
For example, the requirement for miniaturization results in acceleration of technological development for a package having a similar size in relation to a semiconductor chip. Further, the requirement for mounting reliability places importance on packaging technologies that are capable of enhancing efficiency of a mounting process and improving mechanical and electrical reliability after the mounting process is completed. Thus, there have been considerable activities in the development of efficiently packaging a semiconductor chip. As packages that meet the demands, there are a chip scale package (CSP) having a package size substantially equal to that of the semiconductor chip, a multi-chip package (MCP) in which multiple semiconductor chips are incorporated into a single package, and a package-on-package (POP) in which multiple packages are stacked and combined into a single-piece member.
In pace with the development of technology, in response to an increase in storage capacity required for memory and the like, stacked type semiconductor devices (multichip devices) have been proposed which have semiconductor integrated circuit chips stacked together. Namely, a stacked type semiconductor device formed of at least two stacked semiconductor integrated circuit devices is provided, each of which is formed with a specification and includes a semiconductor integrated circuit chip, wherein each of the semiconductor integrated circuit devices includes a conductor that penetrates the semiconductor integrated circuit device, and the semiconductor integrated circuit devices are electrically connected by the conductors and a value of the specification, including a size of the uppermost semiconductor integrated circuit device or the lowermost semiconductor integrated circuit device is maximum or minimum. Consequently, the stacked type semiconductor device has a plurality of chips stacked in a vertical direction. In the stacked type semiconductor device, the chips are electrically connected together via, for example, through plugs that penetrate the chips. Thus, to select a desired one of the stacked memory chips of the same structure is an important task. If a stacked type semiconductor device is manufactured, chips may be individually subjected to operation tests so that only normal chips can be sorted out and stacked.
HITACHI proposed a method for identifying semiconductor integrated circuit device and the U.S. patent publication number is 20050263605. It proposes providing a plurality of identification elements having the same arrangement and physical parameters for identification. For instance, ELPIDA MEMORY INC. disclosed a stacked type semiconductor memory device and chip selection circuit and the U.S. patent publication number is 20070126105. It provides a stacked type semiconductor memory device in which when selecting a desired semiconductor chip among a plurality of stacked semiconductor chips, a plurality of chip identification numbers different from each other can be automatically generated by a plurality of operation circuits connected in cascade, and the desired semiconductor chip can be reliably selected by a unique identification number assigned to each semiconductor chip using the semiconductor chips having the same structure without employing a complicated structure or particular control. In the prior art, a calculated output of an increment circuit of a last stage among M increment circuits connected in cascade may be used to determine the number M of the semiconductor chips. By this, when the number of stacked type semiconductor devices is unknown, the correct number of semiconductor chips can be reliably recognized. A further prior art U.S. Pat. No. 7,494,846 is disclosed by Taiwan Semiconductor Manufacturing Company, Ltd., filed on Mar. 9, 2007. It disclosed a semiconductor structure including a first semiconductor die and a second semiconductor die identical to the first semiconductor die. The first semiconductor die includes a first identification circuit; and a first plurality of input/output (I/O) pads on the surface of the first semiconductor die. The second semiconductor die includes a second identification circuit, wherein the first and the second identification circuits are programmed differently from each other; and a second plurality of I/O pads on the surface of the second semiconductor die. Each of the first plurality of I/O pads is vertically aligned to and connected to one of the respective second plurality of I/O pads. The second semiconductor die is vertically aligned to and bonded on the first semiconductor die.
Furthermore, the Through-Silicon-Via (TSV) technology which offers vertical connection has emerged as a promising solution in 3-D stacked devices. It is a technology where vertical interconnects is formed through the wafer to enable communication among the stacked chips. One of the related articles may refer to IEEE, JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 1, JANUARY 2010, entitled: “8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology”. In the article, a 3-D DRAM with TSVs is proposed which overcomes the limits of conventional module approaches. It also discloses how the architecture and data paths were designed. 3-D technologies including TSV connectivity check and repair scheme, and power noise reduction method are also disclosed. TSVs can be formed simply after fab-out so that no special process integration during the normal process flow is required. Chip identification (ID) is typically assigned.
After the same or different chips are stacked to form a three-dimensional chip, in order to select a desired chip among multiple chips of 3D-IC device to operate, when the system operates, every chip of the 3D-IC device have to be identified a layer-ID (layer identification number) to select the designated chip to operate. Many methods for identifying a layer-ID are proposed in the past. However, they not only increase the cost, but still cannot overcome the problem that the more stacked chips of 3D-IC device, the more electrodes.
The present invention provides a novel method for 3D-IC identify.